A solid-state drive (SSD) is a storage device which typically includes a memory controller attached to non-volatile solid-state memory, typically NAND flash memory, and may communicate with a host to store data received from the host or to retrieve stored data requested by the host. Typically, an SSD controller is linked to an array of NAND flash memory devices arranged as a number of devices on a number of channels, where a number of operations may be conducted in parallel or simultaneously across the number of devices on a number of the channels (memory buses).
During normal operation, the current consumption of an SSD is dependent on many factors, for example, the number and type of operations performed on the SSD.
In normal operation, the SSD controller sends commands (e.g., to perform read data, program data, and erase data operations) on the channels to the NAND flash memory devices. Depending on the commands sent by the SSD controller, the current consumed by the flash memory devices on the channels in question will be in the form of a time-varying waveform, characterized mainly by the type of command. These time-varying waveform characteristics are often in the form of periods of relatively constant low-levels interspersed with very short high current spikes or current peaks. The current spikes are often repeated and cyclical in nature. The frequency, timing, duration, and levels of both the current spikes and the constant low-level current periods on the flash memory devices of the SSD are also dependent on the commands being performed by the SSD, with each command producing a characteristic profile of current spikes and low-level periods.
Further, when an SSD device uses more than one channel, multiple current spikes can occur simultaneously over multiple memory devices on multiple channels, which causes higher current demands and current surges. Higher current demands and current surges are also possible on a single channel where multiple commands are running on multiple memory devices on the single channel at a given time.
One method used to address the variations in current consumption caused by current surges in an SSD is to use bulk capacitors, or other similar energy storage devices, to store the additional energy required to meet the demands of current surges. However, the cumulative effect of simultaneous current surges across multiple channels of an SSD device may increase peak current demand beyond the energy levels that bulk capacitors can provide. Therefore, larger or more capable power supplies may be required for the SSD. In addition, increased peak-power consumption and the cumulative effect of multiple peak-power demands can result in signal integrity problems between the NAND flash memory devices and the SSD controller due to attendant shifts in supply voltages and “ground bounce” (displacement of the zero-voltage (V) reference). Ground bounce is a consequence of the small, but finite, inductances present in voltage supply and ground tracks on the printed circuit board from the voltage regulators to the NAND flash memory devices themselves. Decoupling capacitors placed close to the NAND flash memory devices can be used to ameliorate this unwanted effect, but unfortunately do not eliminate it.
Accordingly, it is advantageous to minimize the influence of current spikes in SSD storage devices in order to reduce peak-power demands and current surges, thereby reducing both (1) the need for large bulk and decoupling capacitors, and (2) the decrease in signal integrity caused by simultaneous current peaks and current surges.
One solution to solve signal integrity problems in SSD storage devices, as taught in U.S. Pat. No. 9,064,059 (“Kim”), has been to apply an offset or delay to the timing of bus transitions, i.e., the data signals on the channels with respect to a common clock in order to eliminate the effect of simultaneous control signals arriving at multiple channels. The logic behind this solution is that a timing delay introduced to one or more channels will result in a reduced likelihood of simultaneous current spikes generated the SSD controller.
However, the solution taught by Kim only addresses the period of switching of the bus signals on the channel between the SSD controller and the flash memory devices, which is the period when a command is sent from the controller to the flash memory device. Once a command is received by the memory device, the bus goes into a quiescent state and the flash memory device internally processes the command. It is during this period of command processing, independent of any further bus activity and where the SSD controller may be free to address another command to another memory device on the same bus, that the flash memory device consumes current with a time varying waveform of sustained current levels and short, sharp, repetitive peaks. Therefore, the solution taught by Kim is incomplete.
Another problem with the above solution taught by Kim is the length of the timing delay itself especially if the delay is based on a high frequency common clock. As shown in FIG. 2, one possible implementation is where the time delays are based on a common clock and a time delay for each channel, dtN, is determined by a time period, dt, multiplied by the channel number, N. The time period, dt, being a fraction of the cycle time of the common clock. As the common clock in FIG. 2 is a 200 MHz clock, For a typical clock frequency in a SSD controller in the 100 s of MHz, the resulting time delays are only a few nanoseconds (ns) in duration, making the solution too short and of no significant difference to the correlation of the current spikes and sustained current levels between multiple commands being processed which occur over much longer time scales, being tens of microseconds (μs) or even milliseconds (ms), depending on the particular flash memory characteristics and the type of commands issued.
Another solution to resolving high power consumption of SSD devices has been restrict the number of channels that can be simultaneously performing commands that have high power demands associated with them, as taught in U.S. Pat. No. 8,745,369 (“Yurzola”). However, Yurzola effectively limits, or chokes, the number of simultaneous commands of the same type in use without specially addressing the problem at hand, i.e., the coincidence or overlap of concurrent high current peaks or current spikes across multiple memory devices resulting in excessive peak-power demands being made by the SSD.